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Sitronix
1. INTRODUCTION
2
ST7578
66 x 102 Dot Matrix LCD Controller/Driver
ST7578 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102-segment and 65-common with 1-icon-common driver circuits. This chip is connected directly to a microprocessor which accepts 3-line or 4-line serial peripheral interface (SPI), I C interface or 8-bit parallel interface. Display data stores in an on-chip display data RAM (DDRAM) of 66 x 102 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Single-chip LCD Controller & Driver Driver Output Circuits 102-segment / 65-common+1-icon-common (1/66 duty) On-chip Display Data Ram Capacity: 66X102= 6,732 bits interface supports Low Power Consumption Analog Circuit Voltage booster (X4, X5) Voltage regulator generates LCD operating voltage (Temperature Gradient: -0.11%/C) Electronic contrast control (255 steps) Voltage follower generates LCD bias voltages (1/4 ~ 1/11 bias) Wide supply voltage range VDD1 - VSS1 : 1.8 ~ 3.3V VDD2 - VSS2 : 2.4 ~ 3.3V
Microprocessor Interface 8-bit parallel bi-directional
6800-series or 8080-series MPU 3-line & 4-line SPI (serial peripheral interface) are available (write only) External RESB (reset) pin Built-in oscillation circuit Oscillator requires no external component
Display supply voltage range Application Vop range : 4V ~ 9.5V Programmable voltage (Vop) : 10.56V (max)
Temperature range: -30 to +85 C Support LCD Module Size up to 1.8"
ST7578
6800 , 8080 , 4-Line , 3-Line interface
Ver 1.2
1/52
2007/04/30
ST7578
3. ST7578 Pad Arrangement
Chip Size: 5570 um x770 um Bump Height: 15 um Chip Thickness: 480 um Bump Pitch: (minimum) PAD Number 1~27, 130~156, 157~163, 243~250 28~129 27~28 129~130 163~164 164~207, 208~211,222~228,229~235,236~242 207~208 211~212 Pitch 37.20 33.00 62.90 60.69 329.57 59.30 131.83 71.30 212~213 213~216,218~221 216~217,217~218 221~222 228~229 235~236 242~243 PAD Number Unit: um Pitch 46.65 33.30 38.80 46.30 66.40 62.45 79.90
* Refer to "Pad Center Coordinates" section for ITO layout.
Fig 1.
Ver 1.2
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2007/04/30
ST7578
Pad Center Coordinates
66 Duty (MY=0)
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN Name COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] SEG[0] SEG[1] SEG[2] X 2695.50 2658.30 2621.10 2583.90 2546.70 2509.50 2472.30 2435.10 2397.90 2360.70 2323.50 2286.30 2249.10 2211.90 2174.70 2137.50 2100.30 2063.10 2025.90 1988.70 1951.50 1914.30 1877.10 1839.90 1802.70 1765.50 1728.30 1665.39 1632.39 1599.39 Y 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 282.75 282.75 282.75
Fig 2. MX=0, MY=0
Ver 1.2
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2007/04/30
ST7578
PAD NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN Name SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] X 1566.39 1533.39 1500.39 1467.39 1434.39 1401.39 1368.39 1335.39 1302.39 1269.39 1236.39 1203.39 1170.39 1137.39 1104.39 1071.39 1038.39 1005.39 972.39 939.39 906.39 873.39 840.39 807.39 774.39 741.39 708.39 675.39 642.39 609.39 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 PAD NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PIN Name SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] X 576.39 543.39 510.39 477.39 444.39 411.39 378.39 345.39 312.39 279.39 246.39 213.39 180.39 147.39 114.39 81.39 48.39 15.39 -17.60 -50.60 -83.60 -116.60 -149.60 -182.60 -215.60 -248.60 -281.60 -314.60 -347.60 -380.60 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
Ver 1.2
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2007/04/30
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PAD NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] X -413.60 -446.60 -479.60 -512.60 -545.60 -578.60 -611.60 -644.60 -677.60 -710.60 -743.60 -776.60 -809.60 -842.60 -875.60 -908.60 -941.60 -974.60 -1007.60 -1040.60 -1073.60 -1106.60 -1139.60 -1172.60 -1205.60 -1238.60 -1271.60 -1304.60 -1337.60 -1370.60 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 PAD NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PIN Name SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] COMS1 COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] X -1403.60 -1436.60 -1469.60 -1502.60 -1535.60 -1568.60 -1601.60 -1634.60 -1667.60 -1728.30 -1765.50 -1802.70 -1839.90 -1877.10 -1914.30 -1951.50 -1988.70 -2025.90 -2063.10 -2100.30 -2137.50 -2174.70 -2211.90 -2249.10 -2286.30 -2323.50 -2360.70 -2397.90 -2435.10 -2472.30 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00
Ver 1.2
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2007/04/30
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PAD NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PIN Name COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[32] COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] VDX2O VDX2O VDX2O VSS T11 T12 BR CP T9 T10 PS2 PS1 PS0 VMO VMO VMO VSS X -2509.50 -2546.70 -2583.90 -2621.10 -2658.30 -2695.50 -2695.50 -2658.30 -2621.10 -2583.90 -2546.70 -2509.50 -2472.30 -2142.72 -2083.42 -2024.11 -1964.81 -1905.50 -1846.19 -1786.89 -1727.58 -1668.28 -1608.97 -1549.67 -1490.36 -1431.06 -1371.75 -1312.45 -1253.14 -1193.84 Y 293.00 293.00 293.00 293.00 293.00 293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 PAD NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 PIN Name VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 RESB CSB RWR ERD A0 VDD1 D7 D6 D5 D4 D3 D2 D1 D0 OSC VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 X -1134.54 -1075.23 -1015.92 -956.62 -897.32 -838.01 -778.70 -719.40 -660.09 -600.79 -541.48 -482.18 -422.88 -363.57 -304.27 -244.96 -185.66 -126.35 -67.05 -7.74 51.56 110.87 170.17 229.47 288.78 348.09 407.39 539.23 598.53 657.84 Y -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
Ver 1.2
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2007/04/30
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PAD NO. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name VSS1 VRS T1 T2 T3 T4 T0 T5 T6 T7 T8 VGO VGO VGI VGI VGI VGI VGS V0O V0O V0I V0I V0I V0I V0S XV0O XV0O XV0I XV0I XV0I X 717.15 788.45 835.10 868.40 901.70 935.00 973.80 1012.60 1045.90 1079.20 1112.50 1158.81 1218.11 1277.42 1336.72 1396.03 1455.33 1514.64 1581.08 1640.38 1699.69 1759.00 1818.30 1877.60 1936.91 1999.36 2058.67 2117.98 2177.28 2236.58 Y -311.50 -311.50 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -309.75 -309.75 -309.75 -309.75 -309.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 PAD NO. 241 242 243 244 245 246 247 248 249 250 PIN Name XV0I XV0S COMS2 COM[60] COM[61] COM[62] COM[63] COM[64] Reserved Reserved X 2295.89 2355.20 2435.10 2472.30 2509.50 2546.70 2583.90 2621.10 2658.30 2695.50 Y -311.50 -311.50 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00
Ver 1.2
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2007/04/30
ST7578
66 Duty (MY=1)
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN Name COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] SEG[0] SEG[1] SEG[2] X 2695.50 2658.30 2621.10 2583.90 2546.70 2509.50 2472.30 2435.10 2397.90 2360.70 2323.50 2286.30 2249.10 2211.90 2174.70 2137.50 2100.30 2063.10 2025.90 1988.70 1951.50 1914.30 1877.10 1839.90 1802.70 1765.50 1728.30 1665.39 1632.39 1599.39 Y 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 282.75 282.75 282.75 PAD NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN Name SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] X 1566.39 1533.39 1500.39 1467.39 1434.39 1401.39 1368.39 1335.39 1302.39 1269.39 1236.39 1203.39 1170.39 1137.39 1104.39 1071.39 1038.39 1005.39 972.39 939.39 906.39 873.39 840.39 807.39 774.39 741.39 708.39 675.39 642.39 609.39 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
Ver 1.2
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2007/04/30
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PAD NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PIN Name SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] X 576.39 543.39 510.39 477.39 444.39 411.39 378.39 345.39 312.39 279.39 246.39 213.39 180.39 147.39 114.39 81.39 48.39 15.39 -17.60 -50.60 -83.60 -116.60 -149.60 -182.60 -215.60 -248.60 -281.60 -314.60 -347.60 -380.60 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 PAD NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] X -413.60 -446.60 -479.60 -512.60 -545.60 -578.60 -611.60 -644.60 -677.60 -710.60 -743.60 -776.60 -809.60 -842.60 -875.60 -908.60 -941.60 -974.60 -1007.60 -1040.60 -1073.60 -1106.60 -1139.60 -1172.60 -1205.60 -1238.60 -1271.60 -1304.60 -1337.60 -1370.60 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
Ver 1.2
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2007/04/30
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PAD NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PIN Name SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] COMS1 COM[64] COM[63] COM[62] COM[61] COM[660 COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] X -1403.60 -1436.60 -1469.60 -1502.60 -1535.60 -1568.60 -1601.60 -1634.60 -1667.60 -1728.30 -1765.50 -1802.70 -1839.90 -1877.10 -1914.30 -1951.50 -1988.70 -2025.90 -2063.10 -2100.30 -2137.50 -2174.70 -2211.90 -2249.10 -2286.30 -2323.50 -2360.70 -2397.90 -2435.10 -2472.30 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 PAD NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PIN Name COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[32] COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] VDX2O VDX2O VDX2O VSS T11 T12 BR CP T9 T10 PS2 PS1 PS0 VMO VMO VMO VSS X -2509.50 -2546.70 -2583.90 -2621.10 -2658.30 -2695.50 -2695.50 -2658.30 -2621.10 -2583.90 -2546.70 -2509.50 -2472.30 -2142.72 -2083.42 -2024.11 -1964.81 -1905.50 -1846.19 -1786.89 -1727.58 -1668.28 -1608.97 -1549.67 -1490.36 -1431.06 -1371.75 -1312.45 -1253.14 -1193.84 Y 293.00 293.00 293.00 293.00 293.00 293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
Ver 1.2
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2007/04/30
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PAD NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 PIN Name VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 RESB CSB RWR ERD A0 VDD1 D7 D6 D5 D4 D3 D2 D1 D0 OSC VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 X -1134.54 -1075.23 -1015.92 -956.62 -897.32 -838.01 -778.70 -719.40 -660.09 -600.79 -541.48 -482.18 -422.88 -363.57 -304.27 -244.96 -185.66 -126.35 -67.05 -7.74 51.56 110.87 170.17 229.47 288.78 348.09 407.39 539.23 598.53 657.84 Y -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 PAD NO. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name VSS1 VRS T1 T2 T3 T4 T0 T5 T6 T7 T8 VGO VGO VGI VGI VGI VGI VGS V0O V0O V0I V0I V0I V0I V0S XV0O XV0O XV0I XV0I XV0I X 717.15 788.45 835.10 868.40 901.70 935.00 973.80 1012.60 1045.90 1079.20 1112.50 1158.81 1218.11 1277.42 1336.72 1396.03 1455.33 1514.64 1581.08 1640.38 1699.69 1759.00 1818.30 1877.60 1936.91 1999.36 2058.67 2117.98 2177.28 2236.58 Y -311.50 -311.50 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -309.75 -309.75 -309.75 -309.75 -309.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
Ver 1.2
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2007/04/30
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PAD NO. 241 242 243 244 245 246 247 248 249 250 PIN Name XV0I XV0S COMS2 COM[4] COM[3] COM[2] COM[1] COM[0] Reserved Reserved X 2295.89 2355.20 2435.10 2472.30 2509.50 2546.70 2583.90 2621.10 2658.30 2695.50 Y -311.50 -311.50 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00
Ver 1.2
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4. BLOCK DIAGRAM
Fig 3.
Block Diagram
Ver 1.2
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5. PINNING DESCRIPTIONS
LCD Driver Output Pins
Pin Name Type LCD segment driver outputs. The display data and the frame control the output voltage. Display data SEG0 to SEG101 O H H L L Frame + + Segment driver output voltage Normal display VG VSS VSS VG VSS Reverse display VSS VG VG VSS VSS 102 Description No. of Pins
Display OFF, Power Save LCD common driver outputs.
The internal scanning signal and the frame control the output voltage. Scan signal COM0 to COM64 O H H L L Frame + + Common driver output voltage Normal display V0 VM VM VSS 2 Reverse display XV0 65
Display OFF, Power Save COMS1,COMS2 (COMS) LCD common driver outputs for icons. O
The output signals of these two pins are the same. When icon feature is not used, these pins should be left open.
Microprocessor Interface Pins
Pin Name Type PS2 PS[2:0] I "L" "H" "L" "H" CSB I PS1 "L" "L" "H" "H" PS0 "L" "L" "L" "L" Description Microprocessor interface select pins. Selected Interface 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface 1 3 No. of Pins
Chip select input pin. Interface access is enabled when CSB is "L". When CSB is non-active (CSB="H"), D[7:0] pins are high impedance. RESB I Reset input pin. When RESB is "L", internal initialization is executed. It determines whether the access is related to data or command. A0 I A0="H" : Indicates that D[7:0] are display data. A0="L" : Indicates that D[7:0] are control data. A0 is not used in 3-Line SPI interface and should fix to "H" by VDD1. 1 1
Ver 1.2
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Pin Name Type PS2 H RWR I L MPU Type 6800 series 8080 series RWR R/W R/W="H": read. R/W="L": write. Write enable input pin. /WR Signals on D[7:0] will be latched at the rising edge of /WR signal. 1 Description Read/Write execution control pin. When PS[1:0]=(H,L), Description Read/Write control input pin. No. of Pins
RWR is not used in serial interfaces and should fix to "H" by VDD1. Read/Write execution control pin. When PS[1:0]=(H,L), PS2 MPU Type ERD Description Read/Write control input pin. H 6800 series R/W="H": When E is "H", D[7:0] are in an E output status. R/W="L": Signals on D[7:0] are latched at the falling edge of E signal. L 8080 series /RD Read enable input pin. When /RD is "L", D[7:0] are in output status. 1
ERD
I
ERD is not used in serial interfaces and should fix to "H" by VDD1. When using 8-bit parallel interface: 6800 or 8080 mode I/O 8-bit bi-directional data bus. Connect to the data bus of 8-bit microprocessor. When CSB is non-active (CSB="H"), D[7:0] pins are high impedance. D[7:0] I When using serial interface: 4-LINE or 3-LINE D[7:4] : Not used and should fix to "H" by VDD1. D[3:1]=SDA : Serial data input, must be connected together. D0=SCLK : Serial clock input. When CSB is non-active (CSB="H"), D[7:0] pins are high impedance. Note: 1. After VDD1 is turned ON, any MPU interface pins cannot be left floating. 8
Clock System Input
Pin Name Type OSC=External clock : and DDRAM circuits. It is not recommended to stop the system clock. When system clock is stopped, the driver outputs (SEGx & COMx) will be hold at the last state (like DC output) and the liquid crystal maybe polarized. To avoid this, never stop system clock before entering Power Down Mode. Description OSC="H" : On-chip oscillator is used. Connect to VDD1 to set OSC="H". Use external clock. Connect external clock to this pin. OSC="L" : Stop system clock. The whole circuit is stopped except the logical OSC I 1 No. of Pins
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Power System Pins
Pin Name VSS1 VSS2 VDX2O VDD1 VDD2 V0 (V0O, V0I, V0S) XV0 (XV0O, XV0I, XV0S) VG (VGO, VGI, VGS) Power Type Power Power Power Power Power Description Digital ground. Connect to VSS2 externally. For pins that are set to be "L", connect them to this power (use VSS1 for "L"). Analog ground. Connect to VSS1 externally. Power for test mode. Left this pin floating. Digital power. If VDD1=VDD2, connect to VDD2 externally. For pins that are set to be "H", connect them to this power (use VDD1 for "H"). Analog power. If VDD1=VDD2, connect to VDD1 externally. LCD driving voltage for commons at negative frame. Power V0 VG > VM > VSS XV0 V0O, V0I & V0S should be separated in ITO layout. V0O, V0I & V0S should be connected together in FPC layout. LCD driving voltage for commons at positive frame. XV0O, XV0I & XV0S should be separated in ITO layout. XV0O, XV0I & XV0S should be connected together in FPC layout. LCD driving voltage for segments. Power VGO, VGI & VGS should be separated in ITO layout. VGO, VGI & VGS should be connected together in FPC layout. 1.24 VG < VDD2. VMO VRS CP Power Power I VM output. LCD driving voltage for commons. 0.62V VM < VDD2. Test pin for monitoring voltage reference level. This pin must be left open (without any kinds of connection). Booster configuration pin for default setting : "L"=4X; "H"=5X. This pin set the default booster stage after reset. Bias circuit configuration pin for default setting : "L"=1/7; "H"=1/9. BR I This pin set the default value of bias ratio after reset. The bias ratio can be changed by software instruction. 1 4 1 1 7 7 7 No. of Pins 4 6 3 5 4
Test Pins
Pin Name T0~T10 T11 T12 Type T T T Must be floating. Do NOT use. Reserved for testing. Must be "L". Connect to VSS1 for pull-low. Do NOT use. Reserved for testing. Must be "H". Connect to VDD1 for pull-high. Description Do NOT use. Reserved for testing. No. of Pins 11 1 1
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Recommend ITO Resistance
Pin Name T[0:10], VRS, VDX2O VDD1, VDD2, VSS1, VSS2 V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VMO A0, RWR, ERD, CSB, D[7:0]
*2 *3 *1
ITO Resistance Floating < 100 < 300 < 1K < 5K < 10K
PS[2:0], OSC , CP, BR, T11, T12 RESB Note: 1. 2. 3. 4. 5.
If using 3-Line or 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 500. If using internal clock, OSC is connect to VDD1 and the limitation of ITO resistance will be "No Limitation". If using external clock, the ITO resistance of OSC should be kept lower than 300 to keep the clock signal quality. To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RESB signal (add a series resistor or increase ITO resistance). The value is different from modules. The option setting to be "H" should connect to VDD1. The option setting to be "L" should connect to VSS1.
Ver 1.2
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ST7578
6. FUNCTIONS DESCRIPTION
Microprocessor Interface
Chip Select Input
CSB pin is used for chip selection. ST7578 can interface with an MPU when CSB is "L". When CSB is "H", the inputs of A0, ERD and RWR with any combination will be ignored and D[7:0] are high impedance. In 3-Line and 4-Line serial interface, the internal shift register and serial counter are reset when CSB is "H".
Parallel / Serial Interface
ST7578 has five types of interface for kinds of MPU, which are three serial and two parallel interfaces. The selection for parallel or serial interface is determined by PS[2:0] pins as shown in table 1.
Table 1. Parallel/Serial Interface Mode
PS2 PS1 PS0 CSB A0 ERD RWR D[7:0] "L" "L" "L" A0 CSB ----Refer to serial interface. "H" "L" "L" --"L" "H" "L" /RD /WR CSB A0 D[7:0] "H" "H" "L" E R/W * The un-used pins are marked as "---" and should be fixed to "H" by VDD1. MPU Interface 4-Line SPI interface 3-Line SPI interface 8080-series parallel interface 6800-series parallel interface
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 as shown in table 2. The data transfer type is determined by signals of A0, ERD and RWR as shown in table 3.
Table 2. Microprocessor Selection for Parallel Interface
PS2 "L" "H" PS1 "H" "H" PS0 "L" "L" CSB CSB A0 A0 ERD /RD E RWR /WR R/W D[7:0] D[7:0] MPU Interface 8080-series 6800-series
Table 3. Parallel Data Transfer
Description A0 E (ERD) R/W (RWR) /RD (ERD) /WR (RWR) "H" "H" "H" "L" "H" Display data read out "H" "H" "L" "H" "L" Display data write "L" "H" "H" "L" "H" Internal status read "L" "H" "L" "H" "L" Writes to internal register (instruction) NOTE: In 6800-series interface mode, fixing E (ERD) pin at high can use CSB as enable signal instead. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0 and R/W (RWR) pins as defined in 6800-series mode. Common 6800-series 8080-series
Setting Serial Interface
Serial Mode PS[2:0] CSB A0 ERD RWR D[7:0] 4-Line SPI interface "L, L, L" A0 CSB ----- ---, ---, ---, ---, SDA, SDA, SDA, SCLK 3-Line SPI interface "H, L, L" --* The un-used pins are marked as "---" and should be fixed to "H" by VDD1.
Note: 1. 2. The option setting to be "H" should connect to VDD1. The option setting to be "L" should connect to VSS1.
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PS2= "L", PS1= "L", PS0= "L" : 4-line SPI interface
When ST7578 is active (CSB="L"), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7578 is not active (CSB="H"), the internal 8-bit shift register and 3-bit counter are reset. The display data/command indication is controlled by the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0 is low. The read feature is not supported in this mode. Serial data on SDA is latched at the rising edge of serial clock on SCLK. After the 8 serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
th
Fig 4.
4-Line SPI Access
PS2= "L", PS1= "L", PS0= "H": 3-line SPI interface
When ST7578 is active (CSB="L"), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7578 is not active (CSB="H"), the internal 8-bit shift register and 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial data, an A0 bit is required to indicate the following 8-bit signals are data or instruction. The read feature is not supported in this mode. Serial data on SDA is latched at the rising edge of serial clock on SCLK. After the 9 serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
th
Fig 5.
3-Line SPI Access
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Data Transfer
ST7578 uses bus holder and internal data bus for data transfer with MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Fig 6. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Fig 7. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signal A0 /WR D0 to D7 Internal signals /WR BUS HOLDER COLUMN ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
Fig 6.
MPU signal A0 /WR /RD D0 to D7 Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS
Data Transfer : Write
N
Dummy
D(N)
D(N+1)
N N
D(N) D(N)
D(N+1) D(N+2) D(N+1) D(N+2)
Fig 7.
Data Transfer : Read
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DISPLAY DATA RAM (DDRAM)
ST7578 contains a 66X102 bit static RAM that stores the display data. The display data RAM (DDRAM) store the dot data for the LCD. It is an addressable array with 102 columns by 66 rows (8-page with 8-bit, 1-page with 1-bit and 1-page with 1-bit). The X-address is directly related to the column output number. Each pixel can be selected when the page and column addresses are specified. The rows are divided into: 8 pages (page 0~7) each with 8 lines (for COM0~63), the 8
th th
page with only 1 line (for COM64) and the 9 page with only 1 line (the 65th row, COMS, for icon). The display data (D7~D0) corresponds to the LCD common-line direction (default: D7 at top when DO=0). Those pages with 8 lines can be accessed through D[7:0] directly. When accessing those pages with fewer than 8 lines, the valid bit(s) in D[7:0] should be checked. Refer to Fig 9 and Fig 10 for detailed illustration. The microprocessor can write to and read from (only Parallel interfaces) DDRAM by the I/O buffer. Since the LCD controller operates independently, data can be written into DDRAM at the same time as data is being displayed without causing the LCD flicker or data-conflict.
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 9 is a special RAM area for the icons and display data is only 1-bit valid (DO=0, D7 is valid; DO=1, D0 is valid).
Line Address Circuit
This circuit controls each line in DDRAM to transfer 102-bit line data to the display data latch circuit. Therefore, the content in DDRAM can be transferred to the segment outputs and the content can be displayed on the LCD module as shown in Fig 13. At the beginning of each LCD frame, the 102-bit RAM data of Line-0 are transferred to the display data latch circuit. At the next line period, the Line Address is increased by one and the 102-bit RAM data at the next line are transferred to the display data latch circuit. The 102-bit icon data are transferred at the last line period during each frame.
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Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the DDRAM. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Register MX and MY makes it possible to invert the relationship between the addresses (Line Address and Column Address) and the outputs (COM/SEG). It is necessary to rewrite the display data into built-in RAM after changing MX setting. The relation between DDRAM and outputs with different MX or MY setting is shown below.
Column Address (Hex) Page Address D3 D2 D1 D0 Data (DO=0) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7
28 29 30 31 32 33 34 35 36 00 01 02 03 04 05 06 07 08 MX=0 MX=1
BBB B B BBB B BBB BBB B B B B B BBB BBBBB B B B B B B BBBB B B B B BBBB B B B B B B BBB B B B B B BBB B B BB B B B B B B B B B B B BB B B BBB B B B B B BBB B B B B B B B B B B B B B B B B B B B B B
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H
COM Output Map PAD No. 1/66 Duty MY=0 MY=1 (COM) COM0 COM64 131 COM1 COM63 132 COM2 COM62 133 COM3 COM61 134 COM4 COM60 135 COM5 COM59 136 COM6 COM58 137 COM7 COM57 138 COM8 COM56 139 COM9 COM55 140 COM10 COM54 141 COM11 COM53 142 COM12 COM52 143 COM13 COM51 144 COM14 COM50 145 COM15 COM49 146 COM16 COM48 147 COM17 COM47 148 COM18 COM46 149 COM19 COM45 150 COM20 COM44 151 COM21 COM43 152 COM22 COM42 153 COM23 COM41 154 COM24 COM40 155 COM25 COM39 156 COM26 COM38 163 COM27 COM37 162 COM28 COM36 161 COM29 COM35 160 COM30 COM34 159 COM31 COM33 158 COM32 COM32 157 COM33 COM31 27 COM34 COM30 26 COM35 COM29 25 COM36 COM28 24 COM37 COM27 23 COM38 COM26 22 COM39 COM25 21 COM40 COM24 20 COM41 COM23 19 COM42 COM22 18 COM43 COM21 17 COM44 COM20 16 COM45 COM19 15 COM46 COM18 14 COM47 COM17 13 COM48 COM16 12 COM49 COM15 11 COM50 COM14 10 COM51 COM13 9 COM52 COM12 8 COM53 COM11 7 COM54 COM10 6 COM55 COM9 5 COM56 COM8 4 COM57 COM7 3 COM58 COM6 2 COM59 COM5 1 COM60 COM4 244 COM61 COM3 245 COM62 COM2 246 COM63 COM1 247 COM64 COM0 248 ICON 130, 243 (COMS1, COMS2)
65 64 63 62 61 60 5F 5E 5D
08 07 06 05 04 03 02 01 00
5D 5E 5F 60 61 62 63 64 65
Line Address (Hex)
1 1
0 0
0 0
0 1
Page 8 Page 9
121 122 123 124 125 126 127 128 129
PAD No. (SEG)
Fig 8.
Relationship between DDRAM and Outputs (COM/SEG)
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ADDRESSING
Data is downloaded in bytes into the Display Data RAM matrix of ST7578 as shown below. The Display Data RAM has a matrix of 66 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 9 (1001) .Addresses outside these ranges are not allowed. In horizontal addressing mode the X address increments after each byte (see Fig 12). After the last X address (X = 101), X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)
Data Structure
Fig 9.
RAM format, if DO=0
Fig 10.
RAM format, if DO=1
Fig 11.
Addressing : Vertical Mode (V=1)
Fig 12.
Addressing : Horizontal Mode (V=0)
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Column Address (Hex) Page Address D3 D2 D1 D0 Data (DO=0) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7
28 29 30 31 32 33 34 35 36 00 01 02 03 04 05 06 07 08 MX=0 MX=1 5D 5E 5F 60 61 62 63 64 65
When the common output is normal
65 64 63 62 61 60 5F 5E 5D
08 07 06 05 04 03 02 01 00
BBB B B BBB B BBB BBB B B B B B BBB BBBBB B B B B B B BBBB B B B B BBBB B B B B B B BBB B B B B B BBB B B BB B B B B B B B B B B B BB B B BBB B B B B B BBB B B B B B B B B B B B B B B B B B B B B B
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H
121 122 123 124 125 126 127 128 129
MY=0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 ICON (COMS)
65 Lines
Line Address (Hex)
1 1
0 0
0 0
0 1
Page 8 Page 9
PAD No. SEG No. (MX=0)
Fig 13.
Display Data RAM Map (66 COM)
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S93 S94 S95 S96 S97 S98 S99 S100 S101
S0 S1 S2 S3 S4 S5 S6 S7 S8
Regardless of the display start line address. Always the last line.
2007/04/30
ST7578
Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. External Power Components The recommended external power components need only 2 capacitors. The detailed values of these two capacitors are determined by the panel size and loading.
IC Internal V0 Generator VG Grnerator VDD2 VSS XV0 Generator
Fig 14.
IC External V0
C2 R1
VG
C1
VSS XV0
C1: 0.1uF~1.0uF (Non-Polar/6V) C2: 0.1uF~1.0uF (Non-Polar/16V) R1: Reserve (Default NC.)
Power Circuit
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7. RESET CIRCUIT
Setting RESB to "L" or RESET instruction can initialize internal function. While RESB is "L", no instruction except read status can be accepted. RESB pin must connect to the reset pin of MPU and initialization by RESB pin is essential before operating. When RESB becomes "L", the following procedures will start. Power Down Mode: PD=1 (Analog Power OFF, Oscillator OFF & COM/SEG output at VSS) Page Address: Y[3:0]=0 Column Address: X[6:0]=0 COM Scan Direction: MY=0 SEG Select Direction: MX=0 Data Orientation: DO=0 Display Control: Display OFF: D=E=0 Basic Instruction Set: H=0 Booster setting: Depends on "CP" setting Initial V0 Setting: VOP[6:0]=0; PRS=0 (Regulator OFF) Bias system: BS[2:0] Depends on "BR" setting After power-on, RAM data are undefined and the display status is "Display OFF". It's better to initialize whole DDRAM (ex: fill all 00h or write the display pattern) before turning the Display ON.
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8. INSTRUCTION TABLE
H=0 or 1 (H-Flag Independent) A0 0 0 0 0 1 1 R/W (RWR) 0 0 0 1 1 0 COMMAND BYTE D7 0 0 0 PD D7 D7 D6 0 0 0 0 D6 D6 D5 0 0 1 0 D5 D5 D4 0 0 MX D D4 D4 D3 0 0 MY E D3 D3 D2 0 0 PD MX D2 D2 D1 0 0 V MY D1 D1 D0 0 1 H DO D0 D0 DESCRIPTION No operation Do not use Power down; entry mode; Select instruction table Read status byte Read data to RAM Write data to RAM INSTRUCTION NOP Reserved Function Set Read Status Read Data Write Data H=0
(Basic Instruction) A0 0 0 0 0 0 0 R/W (RWR) 0 0 0 0 0 0 COMMAND BYTE D7 0 0 0 0 0 1 D6 0 0 0 0 1 X6 D5 0 0 0 0 0 X5 D4 0 0 0 1 0 X4 D3 0 0 1 0 Y3 X3 D2 0 1 D 0 Y2 X2 D1 1 0 0 X Y1 X1 D0 X E X Y0 X0 DESCRIPTION Do not use Sets display configuration Do not use Sets Y address of RAM 0Y9 Sets X address of RAM 0X101
INSTRUCTION Reserved Set V0 Range Display Control Reserved Set Y Address of RAM Set X Address of RAM H=1
PRS V0 range L/H select
(Extended Instruction) A0 0 0 0 0 0 R/W (RWR) 0 0 0 0 0 COMMAND BYTE D7 0 0 0 0 1 D6 0 0 0 1 VOP6 D5 0 0 0 X VOP5 D4 0 0 1 X VOP4 D3 0 1 0 X VOP3 D2 0 DO BS2 X VOP2 D1 X X BS1 X VOP1 D0 X X X DESCRIPTION Do not use Top/bottom row mode set data order Do not use
INSTRUCTION Reserved Display Configuration Bias System Reserved Set V0
BS0 Set bias system (BSx) VOP0 Set VOP parameter to register
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9. INSTRUCTION DESCRIPTION
H=0 or 1
A0 0 Flag MX
(H-Flag Independent)
D7 0 D6 0 D5 1 D4 MX Description SEG bi-direction selection MX=0: normal direction (SEG0->SEG101) MX=1: reverse direction (SEG101->SEG0) COM bi-direction selection MY=0: normal direction (COM0->COM66) MY=1: reverse direction (COM66->COM0) PD=0: chip is active PD=1: chip is in power down mode All LCD outputs at VSS (display off), bias generator and V0 generator off, VOUT can be disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data can be written. Select addressing mode: V=0 for Horizontal Addressing; V=1 for Vertical Addressing. H=0: Basic Instruction set; H=1: Extended instruction set. Data access can be used in both instruction blocks. Refer to the instruction table. D3 MY D2 PD D1 V D0 H
Function Set
R/W(RWR) 0
MY
PD
V H
Read Status
Indicates the internal status of ST7578. A0 R/W(RWR) D7 D6 0 Flag PD PD=0: chip is active PD=1: chip is in power down mode D D,E 0 0 1 1 DO E 0 1 0 1 The bits D and E select the display mode. Display OFF All display segments on Normal mode Inverse video mode 1 PD 0 D5 0 D4 D Description D3 E D2 MX D1 MY D0 DO
DO=0: D7 (MSB) is on top DO=1: D0 (LSB) is on top Refer to page 23.
Read Data
By specify the column address and page address, the display data in DDRAM can be read by MPU (parallel interface). A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 1 1 Read Data
Write Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 1 0 Write Data
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H=0 (Basic Instruction)
Set V0 Range
V0 range L/H select A0 R/W(RWR) 0 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 PRS
PRS=0: V0 programming range LOW PRS=1: V0 programming range HIGH
Display Control
This bits D and E selects the display mode. D7 D6 A0 R/W(RWR) 0 Flag D 0 D,E 0 1 1 E 0 1 0 1 0 0 0 D5 0 D4 0 Description The bits D and E select the display mode. Display OFF All display segments on Normal mode Inverse video mode D3 1 D2 D D1 0 D0 E
Set Y Address of RAM
Y [3:0] defines the Y address vector address of the display RAM. A0 R/W(RWR) D7 D6 D5 D4 0 Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 0 Y1 0 0 1 1 0 0 1 1 0 0 0 Y0 0 1 0 1 0 1 0 1 0 1 1 Content Page0 (display RAM) Page1 (display RAM) Page2 (display RAM) Page3 (display RAM) Page4 (display RAM) Page5 (display RAM) Page6 (display RAM) Page7 (display RAM) Page8 (display RAM) Page9 (display RAM) 0 0 D3 Y3 Allowed X-Range 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 D2 Y2 D1 Y1 Valid Bit D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7 (If DO=0) D0 (if DO=1) D7 (If DO=0) D0 (if DO=1) D0 Y0
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Set X Address of RAM
The X address points to the columns. The range of X is 0...101. A0 R/W(RWR) D7 D6 D5 D4 0 X6 0 0 0 0 : 1 1 1 X5 0 0 0 0 : 1 1 1 0 X4 0 0 0 0 : 0 0 0 1 X3 0 0 0 0 : 0 0 0 X6 X2 0 0 0 0 : 0 1 1 X5 X1 0 0 1 1 : 1 0 0 X0 0 1 0 1 : 1 0 1 X4 D3 X3 Column address 0 1 2 3 : 99 100 101 D2 X2 D1 X1 D0 X0
H=1
(Extended Instruction)
Display Configuration
Top/bottom row mode set data order A0 R/W(RWR) D7 0 Flag DO DO=0: LSB is on top DO=1: MSB is on top Refer to Page 23. 0 0 D6 0 D5 0 D4 0 Description D3 1 D2 DO D1 X D0 X
System Bias
Select LCD bias ratio of the voltage required for driving the LCD. A0 R/W(RWR) D7 D6 D5 D4 0 BS2 0 0 0 0 1 1 1 1 0 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 0 0 Bias 11 10 9 8 7 6 5 4 0 1 D3 0 D2 BS2 D1 BS1 D0 BS0
Recommend LCD Bias Voltage Symbol V0 VG VM VSS Voltage for 1/9 Bias V0 2/9 x V0 1/9 x V0 VSS
* VG range: 1.24V VG < VDD2. * VM range: 0.62V VM < VDD2.
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Set V0:
A0 R/W(RWR) D7 D6 D5 D4 VOP4 D3 VOP3 D2 VOP2 D1 VOP1 D0 VOP0 0 0 1 VOP6 VOP5 The operation voltage V0 can be set by software.
V0=( a + VOPx X b )
(1)
The parameters are explained in table 4. The maximum voltage that can be generated is depending on the VDD2 voltage and the display load current. Two overlapping V0 ranges are selectable via the command "Set V0 Range". For the lower range (PRS=0), a=a1 and for the higher range (PRS=1), a=a2. The voltage steps in both ranges are equal to "b". Note that the internal booster is turned off if VOP[6:0] and the PRS bit are all set to zero. * The Vop must be operated in the range of 4V to 9.5V for the normal or partial display mode application, so that customer have some range(<4V; >9.5V) to adjust contrast by themselves. Table 4 Typical values for parameter for the HV-Generator programming SYMBOL a1 a2 b VALUE 2.94 (PRS=0) 6.75 (PRS=1) 0.03 UNIT V V V
Booster OFF
VOP[6:0] (programmed) {00 hex... 7F hex}
Fig 15.
Setting V0 Voltage
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10. COMMAND SEQUENCE
This section introduces some reference operation flows.
Power ON flow and instruction sequence:
Operating Flow
Power ON Keep RESB=L Wait power stable, t>1ms (depends on system power) Set RESB=H Wait reset finished, t>5us Initial: Power Circuit [ Function Set ] PD=L, H=1 [ Bias System ] [ Set V0 ] [ Function Set ] PD=L, H=0 [ Set V0 Range ] Delay 50ms Initial: LCM Circuit [ Other Settings ] (Address, MX, MY and etc.) Write DDRAM [ Display ON ] Normal Operating
Power Sequence 1. 2. 3. tV2ON: VDD2 power ON delay. => 0 tV2ON No Limitation. tRSTL: Reset Low time after VDD1 is stable. => 0 tRSTL 50 ms . tRW: Reset low pulse width. Please refer to RESB timing specification. Note: 1. 2. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. The specification listed here is to prevent abnormal display on LCD module. Be sure the power is stable and the internal reset is finished (refer to RESB timing specification).
*1
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Power OFF Flow and Sequence
By setting PD="1", ST7578 will go into power save mode. The LCD driving outputs are fixed to VSS, built-in power circuits are turned OFF and a discharge process starts.
Instruction Flow After the built-in power circuits are turned OFF and completely discharged, the power (VDD1 and VDD2) can be removed.
Note: 1. 2. 3. tIPOFF: Internal Power discharge time. => 250ms (max). tV2OFF: Period between VDD1 and VDD2 OFF time. => 0 ms (min). It is NOT recommended to turn VDD1 OFF before VDD2. Without VDD1, the internal status cannot be guaranteed and internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the liquid crystal in panel maybe polarized. 4. 5. 6. 7. 8. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. The timing is dependent on panel loading and the external capacitor(s). The timing in these figures is base on the condition that: LCD Panel Size = 1.4" with C1=1uF, C2=1uF. When turning VDD2 OFF, the falling time should follow the specification: 300ms tPFall 1sec If the power OFF flow cannot meet this specification, it is recommended to use the resistor shown in application circuits (about 500K ~ 1M).
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Power-Save Flow and Sequence
ENTERING THE POWER SAVE MODE The power save mode is achieved by setting PD bit to be "1". No specified instruction flow required. EXITING THE POWER SAVE MODE
INTERNAL SEQUENCE of EXIT POWER SAVE MODE After receiving "PD=0", the internal circuits (Power) will starts the following procedure.
Note: 1. 2. The power stable time is determined by LCD panel loading. The power stable time in this figure is base on: LCD Panel Size = 1.4" with C1=1uF, C2=1uF.
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; please refer to notes 1 and 2. Parameter Digital Power Supply Voltage Analog Power supply voltage LCD Power supply voltage LCD Power driving voltage Operating temperature Storage temperature Symbol VDD1 VDD2 V0-XV0 VG, VM TOPR TSTR Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3~15 -0.3 ~ VDD2 -30 to +85 -65 to +150 Unit V V V V

C C
Notes 1. 2. 3. Stresses above those listed under Limiting Values may cause permanent damage to the device. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Insure the voltage levels of V0, VDD2, VG, VM, VSS and XV0 always match the correct relation: V0 VDD2 > VG > VM > VSS XV0
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12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices.
13. DC CHARACTERISTICS
VDD1=1.8V to 3.3V, VSS=0V; Tamb = -30 C to +85 C; unless otherwise specified. Item Operating Voltage (1) Operating Voltage (2) Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage Input Leakage Current Output Leakage Current Liquid Crystal Driver ON Resistance Frame Frequency Note: 1. 2. Recommend application Vop range : 4V ~ 9.5V. LCD module size : 1.8" (max). Symbol VDD1 VDD2 VIHC VILC VOHC VOLC ILI ILO RON FR Ta=25 C

Condition
Rating Min. 1.7 2.4 0.7 x VDD1 VSS Typ. -- -- -- -- -- -- -- -- 0.7 0.7 75 Max. 3.4 3.4 VDD1 0.3 x VDD1 VDD1 0.2 x VDD1 1.0 3.0 -- -- 80
Unit V V V V V V A A K K Hz
Applicable Pin VDD1 VDD2 MPU Interface MPU Interface D[7:0] D[7:0] MPU Interface MPU Interface COMx SEGx
IOUT=1mA, VDD1=1.8V IOUT=-1mA, VDD1=1.8V
0.8 x VDD1 VSS -1.0 -3.0
Vop=9V, V=0.9V VG=2V, V=0.2V Ta = 25C
-- -- 70
FR default (1,0,0)
Current consumption: During Display, with internal power system, current consumed by whole IC (bare die). Test Pattern Symbol Condition VDD1=VDD2=3.0V, Display Pattern: SNOW (Static) ISS Booster X5 VOP = 9.0 V, Bias=1/9 Ta=25 C Power Down ISS VDD1=VDD2=3.0V, Ta=25 C

Rating Min. Typ. Max.
Unit
Note
--
110
150
A
--
1
10
A
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14. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
(VDD = 3.3V , Ta =-30~85 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D[7:0] RD /WR Signal A0 Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 16 pF CL = 16 pF Condition Min. 80 10 350 70 50 120 50 60 10 -- 10 -- -- 70 50
Max. -- -- -- -- -- --
Unit
ns
(VDD = 2.8V , Ta =-30~85 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D[7:0] RD /WR Signal A0 Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 16 pF CL = 16 pF Condition Min. 120 15 450 120 100 120 100 90 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Unit
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(VDD = 1.8V , Ta =-30~85 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D[7:0] RD /WR Signal A0 Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 16 pF CL = 16 pF Condition Min. 150 30 550 170 150 170 150 120 30 -- 10 -- -- 240 200 Max. -- -- -- -- -- -- ns Unit
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
(VDD = 3.3V , Ta =-30~85 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time D[7:0] E Signal A0 Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 16 pF CL = 16 pF Condition Min. 80 10 240 70 50 70 130 60 10 -- 10 -- -- 70 50
Max. -- -- -- -- -- --
Unit
ns
(VDD = 2.8V , Ta =-30~85 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time D[7:0] E Signal A0 Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 16 pF CL = 16 pF Condition Min. 100 15 340 120 100 120 100 120 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Unit
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(VDD = 1.8V , Ta =-30~85 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time D[7:0] E Signal A0 Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 16 pF CL = 16 pF Condition Min. 150 30 440 170 150 170 150 180 30 -- 10 Max. -- -- -- -- -- -- -- -- -- 240 200 ns Unit
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
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SERIAL INTERFACE (4-Line Interface)
First bit
Last bit
(VDD = 3.3V , Ta =-30~85 C)
Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time
Signal SCLK
Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
Condition
Min. 120 60 60 20 90 20 10 20 120
Max. -- -- -- -- -- -- -- -- --
Unit
A0 SDA CSB
ns
(VDD = 2.8V , Ta =-30~85 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time A0 SDA CSB SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Min. 200 100 100 30 120 30 20 30 150 Max. -- -- -- -- -- -- -- -- -- ns Unit
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(VDD = 1.8V , Ta =-30~85 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time A0 SDA CSB SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Min. 280 140 140 50 150 50 50 40 180 Max. -- -- -- -- -- -- -- -- -- ns Unit
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard.
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SERIAL INTERFACE (3-Line Interface)
First bit
Last bit
(VDD = 3.3V , Ta =-30~85 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Data setup time Data hold time CSB-SCLK time CSB-SCLK time SDA CSB SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Min. 120 60 60 20 10 20 130 Max. -- -- -- -- -- -- --
Unit
ns
(VDD = 2.8V , Ta =-30~85 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Data setup time Data hold time CSB-SCLK time CSB-SCLK time SDA CSB SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Min. 180 90 90 30 20 30 160 Max. -- -- -- -- -- -- --
Unit
ns
(VDD = 1.8V , Ta =-30~85 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Data setup time Data hold time CSB-SCLK time CSB-SCLK time SDA CSB SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Min. 240 120 120 60 50 40 190 Max. -- -- -- -- -- -- -- ns Unit
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard.
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RESET TIMING
tRW
RESB
tR
Internal Status
During Reset ...
Reset Complete
(VDD = 3.3V , Ta =-30~85 C) Item Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 1.5 Max. 1.5 -- Unit us
(VDD = 2.8V , Ta =-30~85 C) Item Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 2.0 Max. 2.0 Unit us
(VDD = 1.8V , Ta =-30~85 C) Item Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 3.0 Max. 3.0 -- Unit us
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1
COM59
250 249 248
Reserved COM64
Reserved
The application circuits are for reference only and actual settings are dependent on LCD module characteristics.
244 25 26 27 COM35 COM34 COM33 242 238-241 236-237 28 SEG0 235 231-234 229-230 228 224-227 222-223 221 220 219 218 217 216 215 214 213 212 208-211 204-207 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 185-188 181-184 180 177-179 176 175 174 173 129 SEG101 172 171 170 169 130 131 132 COMS COM0 COM1 168 167 164-166 243
COM60 COMS
XV0S XV0I XV0O V0S V0I V0O VGS VGI VGO T8 T7 T6 T5 T0 T4 T3 T2 T1 VRS VSS1 VSS2 OSC D0 D1 D2 D3 D4 D5 D6 D7 VDD1 A0 ERD RWR CSB RESB VDD2 VDD1 VSS VMO PS0 PS1 PS2 T10 T9 CP BR T12 T11 VSS VDX2
18
XV0
17
V0
16
VG
15
VSS
14 13 12 11 10 9 8 7
D0 D1 D2 D3 D4 D5 D6 D7
6 5 4 3 2
A0 E R/W CSB RESB
1
VDD
APPLICATION NOTE
Application Circuits
ST7578
163
COM26
156 156 COM25 157
COM31 COM32
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COM59
250 249 248
Reserved Reserved COM64
244 25 26 27 COM33 COM34 242 238-241 236-237 28 SEG0 235 231-234 229-230 228 224-227 222-223 221 220 219 218 217 216 215 214 213 212 208-211 204-207 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 185-188 181-184 180 177-179 176 175 174 173 129 SEG101 172 171 170 169 130 131 132 COMS COM0 COM1 168 167 164-166 COM35 243
COM60 COMS
XV0S XV0I XV0O V0S V0I V0O VGS VGI VGO T8 T7 T6 T5 T0 T4 T3 T2 T1 VRS VSS1 VSS2 OSC D0 D1 D2 D3 D4 D5 D6 D7 VDD1 A0 ERD RWR CSB RESB VDD2 VDD1 VSS VMO PS0 PS1 PS2 T10 T9 CP BR T12 T11 VSS VDX2
18
XV0
17
V0
16
VG
15
VSS
14 13 12 11 10 9 8 7
D0 D1 D2 D3 D4 D5 D6 D7
6 5 4 3 2
A0 /RD /WR CSB RESB
1
VDD
ST7578
163
COM26
156 156 COM25 157
COM31 COM32
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1
COM59
250 249 248
Reserved Reserved COM64
244
COM60 243 COMS
VDD1=VDD2=2.8V
25 26 27 COM33 COM34
COM35
242 238-241 236-237
XV0S XV0I XV0O 235 V0S
10
XV0
OSC : VDD1
T12 : VDD1
BR : VDD1
CP : VDD1
28
SEG0
231-234 229-230 228 224-227 222-223 221 220 219 218 217 216 215 214 213 212 208-211 204-207 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 185-188 181-184 180 177-179 176
V0I V0O VGS VGI VGO T8 T7 T6 T5 T0 T4 T3 T2 T1 VRS VSS1 VSS2 OSC SCLK (D0) SDA (D1) SDA (D2) SDA (D3) D4 D5 D6 D7 VDD1 A0 ERD RWR CSB RESB VDD2 VDD1 VSS VMO PS0
PS0 : Vss
PS1 : Vss
PS2 : Vss
9
V0
T11 : Vss
8
VG
7
VSS
6
SCLK
(bias ratio can be changed by instruction)
Resolution : 66(65COM+ICON)*102(SEG)
5
SDA
4
A0
3 2
CSB RESB
1
VDD
Bias ratio default : 1/9
Internal analog circuit
175 174 173 129 SEG101 172 171 170 169 168
PS1 PS2 T10 T9 CP BR T12 T11
Interface : 4-Line SPI
ST7578
Internal OSC
130
COMS
Booster : X5
131
COM0
167
VSS
Vop=8.76V
132
COM1
164-166
VDX2
C=0.1uF
ST7578
163
COM26
156 156 COM25 157
COM31 COM32
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1
COM59
250 249 248
Reserved Reserved COM64
244 25 26 27 COM33 COM34 242 238-241 236-237 28 SEG0 235 231-234 229-230 228 224-227 222-223 221 220 219 218 217 216 215 214 213 212 208-211 204-207 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 185-188 181-184 180 177-179 176 175 174 173 129 SEG101 172 171 170 169 130 131 132 COMS COM0 COM1 168 167 164-166 COM35 243
COM60 COMS
XV0S XV0I XV0O V0S V0I V0O VGS VGI VGO T8 T7 T6 T5 T0 T4 T3 T2 T1 VRS VSS1 VSS2 OSC SCLK (D0) SDA (D1) SDA (D2) SDA (D3) D4 D5 D6 D7 VDD1 A0 ERD RWR CSB RESB VDD2 VDD1 VSS VMO PS0 PS1 PS2 T10 T9 CP BR T12 T11 VSS VDX2
9
XV0
8
V0
7
VG
6
VSS
5
SCLK
4
SDA
3 2
CSB RESB
1
VDD
ST7578
163
COM26
156 156 COM25 157
COM31 COM32
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Selection of Application Voltage
Power Range Summary l l l l Positive Booster: (VDD2 x PCn x BE) V0 or (VDD2 x PCn x BE) Vop; Negative Booster: [-VDD2 x (PCn - 1) x BE] XV0 or [VDD2 x (PCn - 1) x BE] (Vop - VG), where VG = Vop x 2 / N; Vop requirement: [VDD2 x (PCn - 1) x BE] [Vop x (N - 2) / N] or [Vop VDD2 x (PCn - 1) x BE x N / (N - 2)]. PCn is the booster stage and BE is the booster efficiency. Referential values are listed below: (assume VDD2=2.4V) Module Size 1.4": BE=80% (min); Module Size = 1.4"~1.8": BE=76% (min). Actual BE should be determined by module loading and ITO resistance value. l l l 1.24 VG < VDD2. Recommend VG is: VDD2-VG around 0.5~0.8V. VM=VG/2 and 0.62V VM < VDD2. The worse condition should be considered: Low temperature effect and display on with snow pattern on panel (max: 1.8"). Referential LCD Module Setting VDD1=VDD2=2.8V, Panel Size=1.4" Duty 1/66 Booster 5X, CP=H Vop 8.49V ~ 9V, PRS=1 Bias 1/9, BS[2:0]=0,1,1
Note: It is recommended to reserve some range for user adjustment and temperature effect.
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ITO Layout Reference
FPC PIN
FPC PIN
FPC PIN
FPC PIN
FPC PIN
FPC PIN
FPC FPC FPC PIN PIN PIN
FPC FPC FPC PIN PIN PIN
FPC FPC FPC PIN PIN PIN
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Manual Alignment by ITO Layout
Optional ITO alignment mark for manual COG machine (reference ITO mark).
Upper-Left Corner ITO
Upper-Right Corner ITO
ITO Lower-Left Corner
ITO Lower-Right Corner
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Reversion History
Version
1.0 1.1
Date
2007/01/18 2007/02/28 Formal release. l l l l l l l l l
Description
Modify reset feature description. Separate I C interface as ST7578i. Add operating flows and power sequences. Add application note for Vop selection and power setting. Add Temperature Gradient of Regulator. Update ITO Resistance suggestion: No Limitation => 5K. Rearrange Microprocessor Interface section. More detailed application circuits. Fix typing mistake.
2
1.2
2007/4/30
Ver 1.2
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